Method and system for verification of soft error handling with application to CMT processors
US7320114B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 2, 2005 |
| Grant date | Jan 15, 2008 |
| Priority date | — |
| Expiry date | Jan 8, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/261
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method provides for verifying soft error handling in an integrated circuit (IC) design. A diagnostic program is executed on a virtual IC based on the IC design using a simulator. A soft error is injected into the virtual IC to trigger hardware error correction in the virtual IC and a software exception. A record of a type and a location of the soft error at the time of the injecting is created. The error log generated by hardware error correction is then compared with the record of injected error, the hardware error correction being part of the virtual IC. An IC design flaw is indicated when a discrepancy exists between the error log and the record of the injected error.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.