P-domino register with accelerated non-charge path
US7321243B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 16, 2006 |
| Grant date | Jan 22, 2008 |
| Priority date | — |
| Expiry date | Jul 13, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/356165
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A P-domino register has a domino stage, a write stage, an inverter, a high keeper path, a low keeper path, and an output stage. The domino stage evaluates a logic function based on at least one input data signal and a pulsed clock signal. The pulsed clock signal lags a symmetric clock signal. The domino stage pre-discharges a pre-discharged node low when the symmetric clock signal is high and opens an evaluation window when the pulsed clock signal goes low, and pulls the pre-discharged node high if it evaluates, and keeps the pre-discharged node low if it fails to evaluate. The output stage provides an output signal based on states of the pre-discharged node and a second preliminary output node.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.