Programmable logic enabled dynamic offset cancellation
US7321259B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 6, 2005 |
| Grant date | Jan 22, 2008 |
| Priority date | — |
| Expiry date | Jan 28, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2203/45702
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Techniques and circuitry are provided for programmatically controlling signal offsets in integrated circuitry. In one embodiment, a buffer circuit having an offset cancellation circuit receives a signal and transmits the signal to programmable logic circuit. The programmable logic uses programmable resources and/or one or more algorithms to measure integrated circuit operations and/or operational errors associated with the offset. The control signal is fed back to an input of the offset cancellation circuit. In one embodiment, the offset cancellation circuit adjusts the offset of the signal in response to the magnitude of the offset cancellation signal received until changes associated with the offset and/or the magnitude of the operational errors are no longer attributable to the offset.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.