Method and system for reducing bit error rate in a high-speed four to one time domain multiplexer
US7321603B1 · kind B1 · utility
1Cited by
11References
18Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Apr 3, 2002 |
| Grant date | Jan 22, 2008 |
| Priority date | — |
| Expiry date | May 3, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K17/6264
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Method and system for reducing bit error rate (BER) in a high-speed four-to-one time domain multiplexer are disclosed. In one embodiment of the present invention, a keep-alive current is employed in the latches of a four-to-one multiplexer in order to minimize the BER. By adjusting the keep-alive current of the latches in the datapath of the multiplexer, the latch performance can be optimized, thereby achieving minimum BER. Moreover, better latch performance can immunize the multiplexer against small timing misalignment.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.