Method and apparatus for variable sigma-delta modulation
US7321634B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 17, 2004 |
| Grant date | Jan 22, 2008 |
| Priority date | — |
| Expiry date | Aug 10, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M7/3015
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for modulating a digital input signal is disclosed. The digital input signal is partitioned into a less-significant bit signal and a more-significant bit signal. A lower-order modulation of the less-significant bit signal is performed to generate an intermediate output signal. The intermediate output signal is appended to the more-significant bit signal to form an intermediate input signal. A higher-order modulation of the intermediate input signal is performed to generate a digital output signal. The higher-order modulation is of an order higher than the lower-order modulation. A phase-locked loop using the method and apparatus is disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.