Drift compensation system and method in a clock device of an electronic circuit
US7321648B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 30, 2004 |
| Grant date | Jan 22, 2008 |
| Priority date | — |
| Expiry date | May 11, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/089
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A drift compensation system includes a first clock phase alignment circuit adapted for providing an output clock signal which is frequency locked to an input reference clock signal; a second clock phase alignment circuit identical to the first clock phase alignment circuit but wherein the reference clock signal is the output clock signal provided by the first clock phase alignment circuit; first deviation means at the output of the first clock phase alignment circuit for providing a first deviation between its current clock phase and its initial clock phase; second deviation means at the output of the second clock phase alignment circuit for providing a second deviation between its current clock phase and its initial clock phase; and a phase control logic adapted for providing first phase shift signals as inputs to the first clock phase alignment circuit in order to cancel the phase shift between the output clock signal and the reference clock signal in response to the difference between the first and the second deviations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.