Highly available system test mechanism
US7321948B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 30, 2005 |
| Grant date | Jan 22, 2008 |
| Priority date | — |
| Expiry date | Aug 20, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/006
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Boards in a system are interconnected by a first set of signals including a first control signal and first function signals. Each board in the system includes a second set of signals corresponding to the first set of signals. When the first control signal and a first function signal are asserted, the corresponding second signals of are asserted in response and a function is performed on the boards. But, if any of the second signals are asserted, none of the first signals is asserted in response. Test signals on boards are thereby isolated from test signals coupled to all the boards on the system, so a fault on any signal in any second set of signals will not propagate to the first set of signals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.