System and method for sharing memory by heterogeneous processors
US7321958B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 30, 2003 |
| Grant date | Jan 22, 2008 |
| Priority date | — |
| Expiry date | Oct 8, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/1652
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system for sharing memory by heterogeneous processors, each of which is adapted to process its own instruction set, is presented. A common bus is used to couple the common memory to the various processors. In one embodiment, a cache for more than one of the processors is stored in the shared memory. In another embodiment, some of the processors include a local memory area that is mapped to the shared memory pool. In yet another embodiment, local memory included on one or more of the processors is partially shared so that some of the local memory is mapped to the shared memory area, while remaining memory in the local memory is private to the particular processor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.