Method and apparatus to change the operating frequency of system core logic to maximize system memory bandwidth
US7321979B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 22, 2004 |
| Grant date | Jan 22, 2008 |
| Priority date | — |
| Expiry date | Aug 11, 2025 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method, apparatus, and computer instructions for changing an operating frequency for a system core logic used to interface to memory in the multi-processor data processing system. A determination is made as to whether the operating frequency should be changed from a default frequency to another frequency. Slave processors are placed in the multi-processor data processing system into a non-transactional mode, in response to determining the operating frequency should be changed from the default operating frequency to the another operating frequency. When the slave processors are in the non-transactional mode, the operating frequency is changed in the system core logic to other operating frequency by the master processor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.