Configuring cache memory from a storage controller
US7321986B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 31, 2004 |
| Grant date | Jan 22, 2008 |
| Priority date | — |
| Expiry date | Sep 28, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/601
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed are a storage controller, and a method of operating a storage controller, for interfacing between host systems and a storage devices system. The storage controller includes a first cluster including a first processor and a first cache, and a second cluster including a second processor and a second cache. The method comprises the step of directing data from the host systems through first and second data paths to the storage system. The first processor and cache are associated with the first data path, and the second processor and cache are associated with the second data path. Under one set of conditions, the controller enters a failover mode, wherein data directed to the first data path are routed to the second data path. Under another set of conditions, the controller deconfigures the first cache without entering the failover mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.