Circuit layout and semiconductor substrate for photosensitive chip
US7322020B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 25, 2005 |
| Grant date | Jan 22, 2008 |
| Priority date | — |
| Expiry date | Mar 11, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10F39/811
Abstract
A circuit layout for a photosensitive chip includes a semiconductor substrate, a plurality of first circuit lines and a plurality of second circuit lines. The semiconductor substrate has a matrix of photosensitive units. Each photosensitive unit has a first blocking region, a second blocking region and a photosensitive region formed on the semiconductor substrate. The first blocking region is formed between neighboring photosensitive regions aligned in a vertical direction. The second blocking region is formed between neighboring photosensitive regions aligned in a horizontal direction. Free electrons produced by illuminating the photosensitive units are blocked by the first and the second blocking regions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.