Method of fabricating electronic component using resist structure with no undercut
US7323112B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 29, 2003 |
| Grant date | Jan 29, 2008 |
| Priority date | — |
| Expiry date | Jun 24, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01J2237/3114
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A method for milling a structure. A single- or multi-layer resist having no undercut is added to a surface of a structure to be milled, the surface to be milled defining a plane. A milling process, such as ion milling, is performed. The milling process includes milling the structure at high incidence and milling the structure at razing incidence. The milling process can be performed only once, or repeated multiple times. High incidence can be defined as about 65 to about 90 degrees from the plane of the surface being milled. Razing incidence can be defined as about 0 to about 30 degrees from the plane of the surface being milled.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.