Thin film resistor integration in a dual damascene structure
US7323751B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 3, 2003 |
| Grant date | Jan 29, 2008 |
| Priority date | — |
| Expiry date | Jun 3, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A thin film resistor and at least one metal interconnect are formed in an integrated circuit. A first dielectric layer is formed over a metal interconnect layer. A thin film resistor is formed on the first dielectric layer and a second dielectric layer formed over the thin film resistor. Thin film resistor vias and the at least one trench are formed concurrently in the second dielectric layer. A trench via is then formed in the at least one trench. The trench via, the at least one trench and the thin film resistor vias are filled with a contact material layer to form thin film resistor contacts and at least one conductive line coupled to the metal interconnect layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.