Multiphase divider for P-PLL based serial link receivers
US7323913B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 12, 2007 |
| Grant date | Jan 29, 2008 |
| Priority date | — |
| Expiry date | Oct 12, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K23/00
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A multiphase divider includes a plurality of resetable dividers configured for performing resetable divider stages to a plurality of multiphase signals forming a plurality of divided multiphase signals having a monotonic increasing phase with equal spacing and an ideal duty cycle of 50%, wherein the plurality of divided multiphase signals have no phase ambiguity; and a reset signal generator configured for producing a plurality of periodic reset signals to the plurality of resetable dividers to enable the plurality of resetable dividers to divide the plurality of multiphase signals in a timely correct sequence to form the divided multiphase signal, the plurality of periodic reset signals being produced by a combinational network of the reset signal generator, the combinational network is configured for generating a number of pulses based on the plurality of multiphase signals and performing decimation stages to reduce the number of pulses within the pulse traces.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.