Lock detect circuit for a phase locked loop
US7323946B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 20, 2005 |
| Grant date | Jan 29, 2008 |
| Priority date | — |
| Expiry date | Jan 4, 2026 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S331/02
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An improved system and method for determining the lock condition of a Phase Locked Loop (PLL) is described. The lock detect circuit generates a fast lock detect signal that may be used to detect a transient loss of lock. The lock detect circuit may also include a phase alignment detect circuit to detect a misalignment in the phase of a reference clock and a feedback clock. Additionally, the lock detect circuit may include a reference clock detect circuit to detect if the reference clock signal is detected. Output signals from all of the above circuits may be communicated to a logic circuit in order to create an enhanced lock detect signal. An extended lock detect signal may also be communicated to the logic circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.