Multiple stage delta sigma modulators
US7324030B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 29, 2006 |
| Grant date | Jan 29, 2008 |
| Priority date | — |
| Expiry date | Sep 29, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M7/3022
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A delta sigma modulator which employs a plurality of accumulators with non-power-of-2 modulus. The accumulators may consist of a primary non-power-of-2 modulus accumulator and a secondary non-power-of-2 modulus accumulator. The number of bits in the primary accumulators affects the frequency resolution of the resultant delta sigma fractional N frequency synthesizer and can be the minimum number of bits required by the resolution specification. The secondary accumulator integrates the carry outputs of its corresponding primary accumulators. This integration results in attenuating the dc content of the modulator output by a factor equal to the modulus of the secondary accumulators and may require compensation in the recombination block.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.