Methods and apparatus to balance reference settling in switched-capacitor pipelined digital to analog converter
US7324034B2 · kind B2 · utility
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19References
18Claims
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Key dates
| Filing date | Sep 22, 2004 |
| Grant date | Jan 29, 2008 |
| Priority date | — |
| Expiry date | Sep 22, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/72
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The linearity of switched-capacitor, pipeline digital to analog converters is improved by balancing the settling behavior of its pre-charge switches. In more detail, a switched capacitor DAC includes a number of substantially identical cells, one cell for each bit of an input digital word. A number of switch driver circuits are used to apply respective switch control signals to turn respective switches on and off. Advantageously, the switch control signals differ by an amount determined to equalize the gate-to-source voltage difference between different switches.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.