Memory device and method of operating the same with high rejection of the noise on the high-voltage supply line
US7324379B2 · kind B2 · utility
2Cited by
5References
27Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 30, 2005 |
| Grant date | Jan 29, 2008 |
| Priority date | — |
| Expiry date | Jan 23, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/30
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device has an array of memory cells. A column decoder is configured to address the memory cells. A charge-pump supply circuit generates a boosted supply voltage for the column decoder. A connecting stage is arranged between the supply circuit and the column decoder. The connecting stage switches between a high-impedance state and a low-impedance state, and is configured to switch into the high-impedance state in given operating conditions of the memory device, in particular during a reading step.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.