Low power high density random access memory flash cells and arrays
US7324387B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 2, 2007 |
| Grant date | Jan 29, 2008 |
| Priority date | — |
| Expiry date | Apr 2, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Low power high density random access memory flash cells and arrays using Fowler Nordheim (FN) tunneling for both programming and erasing. The memory array is divided into sectors, each sector comprising a predetermined number of rows. The bit lines are similarly segmented, each global bit line being selectively connectable to a local bit line for each sector, each local bit line being connected to the drains of all floating gate cells in a respective column of each sector. The sources of all floating gate cells in a respective column of each sector are connected to a local source line for that sector, the local source lines for each sector being controllably connectable to respective global source lines. Consequently all floating gate cells within a column of a sector are connected in parallel, source to source and drain to drain. Representative programming and erase voltages not disturbing other cells are disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.