High speed decoder
US7324614B2 · kind B2 · utility
6Cited by
4References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 18, 2002 |
| Grant date | Jan 29, 2008 |
| Priority date | — |
| Expiry date | Nov 23, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/41
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A branch metric duplication method substantially reduces interconnection delays. The branch metric duplication method is particularly useful to implement a high speed radix-4 Viterbi decoder targeted for FPGA applications. The decoder includes a plurality of branch metric computation units (BMCUs), at least one add-compare-select unit (ACSU) having a plurality of cells, and a survivor path memory unit (SMU). The plurality of BMCUs, the at least one ACSU, and the SMU are configured to implement the decoder.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.