Methods and apparatus for testing a link between chips
US7324913B2 · kind B2 · utility
20Cited by
6References
5Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 1, 2006 |
| Grant date | Jan 29, 2008 |
| Priority date | — |
| Expiry date | Feb 1, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/31717
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
In a first aspect, a first method of testing a link between a first chip and a second chip is provided. The first method includes the steps of, while operating in a test mode, (1) transmitting test data of sufficient length to enable exercising of worst case transitions from the first chip to the second chip via the link; and (2) performing cyclic redundancy checking (CRC) on the test data to test the link. Numerous other aspects are provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.