Method and apparatus for automated debug and optimization of in-circuit tests
US7324982B2 · kind B2 · utility
6Cited by
4References
6Claims
0Family size
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Key dates
| Filing date | May 5, 2004 |
| Grant date | Jan 29, 2008 |
| Priority date | — |
| Expiry date | Oct 14, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/2257
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method and apparatus for automatically debugging and optimizing an in-circuit test that is used to test a device under test on an automated tester is presented. The novel test debug and optimization technique extracts expert knowledge contained in a knowledge framework and automates the formulation of a valid stable, and preferably optimized, test for execution on an integrated circuit tester.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.