Hierarchical interconnect for configuring separate interconnects for each group of fixed and diverse computational elements
US7325123B2 · kind B2 · utility
13Cited by
36References
46Claims
0Family size
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Key dates
| Filing date | Mar 7, 2003 |
| Grant date | Jan 29, 2008 |
| Priority date | — |
| Expiry date | Sep 26, 2023 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit having computational elements. As least one of the computational elements has a fixed architecture. An interconnection network is coupled to a first group of the computational elements to configure the first group for a first operation. An interconnection network is coupled to a second group of computational elements to configures the second group for a second operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.