Semiconductor device incorporating thyristor-based memory and strained silicon
US7326969B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 2, 2004 |
| Grant date | Feb 5, 2008 |
| Priority date | — |
| Expiry date | Jul 25, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/201
Abstract
A semiconductor memory device may comprise a thyristor-based memory having some portions formed in strained silicon, and other portions formed in relaxed silicon. In a further embodiment, a thyristor in the thyristor-based memory may be formed in a region of relaxed silicon germanium, while an access device to the thyristor-based memory may have a body region incorporating a portion of a layer of strained silicon. In yet a further embodiment, different regions of the thyristor may be formed in vertical aligned relationship relative to an upper surface of the relaxed silicon germanium. For this embodiment, the thyristor may be formed substantially within the depth of the relaxed silicon germanium layer. In a method of forming the semiconductor device, relaxed silicon may be deposited over exposed regions of a silicon substrate, and a thin layer of strained silicon formed over a portion of the substrate having silicon germanium.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.