Multi-surfaced plate-to-plate capacitor and method of forming same
US7327011B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 2, 2005 |
| Grant date | Feb 5, 2008 |
| Priority date | — |
| Expiry date | Jan 10, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A plate to plate capacitor has a first plate, a second plate, and an insulating medium separating the first plate from the second plate. The first plate and the second plate are adapted and arranged to form an interlaced structure in which multiple capacitance surface areas in different planes, such as horizontal and vertical, are provided between said first and second plates. The plate to plate capacitor can be formed as a stack of layers in which one or more alternating first and third insulating layers each have first and second conductive lines configured therein and in which one or more second insulating layers having conductive vias formed therein interpose respective first and third insulating layers. The first and second conductive lines in the first insulating layer(s) are interconnected by the conductive vias to the first and second conductive lines, respectively, in the third layer(s) so as to interlace the first and second metal conductive lines together.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.