High performance, low leakage SRAM device and a method of placing a portion of memory cells of an SRAM device in an active mode
US7327598B2 · kind B2 · utility
6Cited by
7References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 10, 2004 |
| Grant date | Feb 5, 2008 |
| Priority date | — |
| Expiry date | Nov 10, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An SRAM device and a method of placing a portion of memory cells of an SRAM device in an active mode is provided. In one embodiment, the SRAM device includes a hierarchical grouping of memory cells of memory cells and biasing circuitry, coupled to the hierarchical grouping of memory cells, configured to bias a subset of the set based on a memory address associated therewith. In another embodiment, a method includes receiving a memory address associated with the hierarchical grouping of memory cells and biasing a subset of the hierarchical grouping of memory cells based on the memory address.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.