Technique for reducing traffic in an instruction fetch unit of a chip multiprocessor
US7328327B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 11, 2006 |
| Grant date | Feb 5, 2008 |
| Priority date | — |
| Expiry date | Mar 19, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3885
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor includes a fetch pipeline, out-of-order (OOO) logic and a strand selector. The fetch pipeline is configured to provide instructions from an instruction store to a fetch buffer responsive to receiving a plurality of fetch requests for a first strand, selected from a plurality of active strands. The OOO logic is coupled to the fetch pipeline and is configured to detect an OOO packet in the fetch pipeline in response to the fetch requests for the first strand. The strand selector is coupled to the OOO logic and the fetch pipeline and selects a second strand for processing in the fetch pipeline, from the active strands, when the OOO logic detects the OOO packet associated with the first strand.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.