Circuit and method for testing embedded phase-locked loop circuit
US7328383B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 27, 2006 |
| Grant date | Feb 5, 2008 |
| Priority date | — |
| Expiry date | Sep 27, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11B20/1403
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
In a method for testing an embedded phase-locked loop (PLL) circuit, a first clock signal is provided to an embedded phase-locked loop (PLL) circuit to be tested. A PLL clock signal of a first frequency is generated by the embedded PLL in response to the first clock signal. The PLL clock signal of the first frequency is sampled with a second clock signal of a second frequency to generate a first sampled signal, wherein the second frequency is different from the first frequency but has a first correlation with the first frequency so that the first sampled signal toggles at a predetermined frequency when the embedded PLL circuit is in a normal operation condition. The embedded PLL circuit is determined to be in an abnormal operation condition if the first sampled signal does not toggle at said predetermined frequency.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.