Error correction within a cache memory
US7328391B2 · kind B2 · utility
13Cited by
4References
38Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 1, 2004 |
| Grant date | Feb 5, 2008 |
| Priority date | — |
| Expiry date | Jan 17, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1064
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A cache memory includes error bits corresponding to each line of data. An error detecting circuit uses these error bits to detect if a soft error has occurred within the data of a cache line. If such an error has occurred, then the line may be refilled from the main memory or some other action taken, such as a write back or generation of a soft error abort signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.