Modeling blocks of an integrated circuit for timing verification
US7328415B2 · kind B2 · utility
2Cited by
6References
24Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 20, 2001 |
| Grant date | Feb 5, 2008 |
| Priority date | — |
| Expiry date | Feb 3, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/3312
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit may be divided into blocks and analyzed using a modeling algorithm which facilitates the concurrent analysis of a plurality of blocks forming an integrated circuit. In some cases, an electrical connectivity description of a block may be utilized to create static-timing representations that contain the logic that communicates with the boundary of a block. Once the models for the blocks forming an integrated circuit are generated, static-timing analysis may take place concurrently with all the relevant, identified paths.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.