Method and system for timing modeling for custom circuit blocks
US7328416B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 24, 2005 |
| Grant date | Feb 5, 2008 |
| Priority date | — |
| Expiry date | Mar 3, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/3312
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method is provided for modeling timing characteristics of a circuit block of an integrated circuit, which includes a main circuit and a timing circuit. The method comprises determining an output pin output delay and determining a timing circuit delay. The output pin output delay is an interval of time from a clock signal reaching a clock reference point (CRP) to an output signal arriving at the output pin. The clock reference point is positioned between the timing circuit and the main circuit. The timing circuit delay is an interval of time from a clock signal arriving at a clock input pin to a clock signal arriving at the CRP. The determination of the timing circuit delay is based on a computer simulation of a netlist of circuit elements in the timing circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.