Circuit with high power density applicability
US7330055B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 26, 2005 |
| Grant date | Feb 12, 2008 |
| Priority date | — |
| Expiry date | Apr 10, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K17/79
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A power control circuit is presented. The circuit includes a pair of parallel optocoupler/logic stages and a pair of parallel voltage-to-current driver stages electrically coupled to a halfbridge stage in the order described. An input signal is communicated to the optocoupler/logic stage and processed therein to produce two distinctly separate but complimentary waveforms. Complimentary waveforms are communicated to the voltage-to-current driver stage to drive a paired arrangement of JFET switches. Thereafter, the JFET switches communicate with the halfbridge stage to control function of BJT switches. BJT switches are sequenced to produce a high power output. The present invention has immediate applicability to power conditioning, control, and distribution systems, as well as other applications which include or rely on silicon power transistors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.