Method and apparatus for correcting the duty cycle of a digital signal
US7330061B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 1, 2006 |
| Grant date | Feb 12, 2008 |
| Priority date | — |
| Expiry date | Jul 21, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/1565
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The disclosed methodology and apparatus measure and correct the duty cycle of a reference clock signal that a clock circuit supplies to a duty cycle measurement (DCM) circuit. In one embodiment, the DCM circuit includes a capacitor driven by a charge pump. The reference clock signal drives the charge pump. The clock circuit varies the duty cycle of the reference clock signal among a number of known duty cycle values. The DCM circuit stores resultant capacitor voltage values corresponding to each of the known duty cycle values in a data store. The DCM circuit applies a test clock signal having an unknown duty cycle to the capacitor via the charge pump, thus charging the capacitor to a new voltage value that corresponds to the duty cycle of the test clock signal. Control software accesses the data store to determine the duty cycle to which the test clock signal corresponds, thus providing a measured duty cycle. The apparatus generates an error signal when the measured duty cycle varies from a predetermined duty cycle. The apparatus includes a variable duty cycle clock generator that alters the duty cycle of the test clock signal to reduce the error.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.