Semiconductor memory device
US7330386B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 25, 2006 |
| Grant date | Feb 12, 2008 |
| Priority date | — |
| Expiry date | Jul 25, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2227
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a memory cell array, source lines are provided so that each of the source line is connected to ones of memory cells which belong to adjacent two rows and a plurality of source bias control circuits for supplying a source bias potential which is higher than a ground potential and lower than a power supply potential are provided so as to correspond to the source lines, respectively. During a stand-by period, each of the source lines is controlled to be in a state where the source bias potential is supplied and, during an active period, one or more of the source lines which are not connected to one of the memory cells which is to be read out are controlled to be in a state where the source bias potential is supplied.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.