Sense amplifier circuit and method of operation
US7330388B1 · kind B1 · utility
25Cited by
37References
20Claims
0Family size
Assignee
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Key dates
| Filing date | Sep 23, 2005 |
| Grant date | Feb 12, 2008 |
| Priority date | — |
| Expiry date | Jun 17, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4094
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one arrangement, a semiconductor memory device can include a sense amplifier circuit (300) having drive high transistors (P30/P31), drive low transistors (N31/N32) and equalization transistors (N33-N35). Such transistors can have a body bias (VbiasN, VbiasP) that varies according to the operation conditions of the semiconductor memory device. Such variations can include any of: manufacturing process variations, operating temperature, or operating voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.