Complementary code keying (CCK) sequentially decoding apparatus and process thereof
US7330522B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 7, 2004 |
| Grant date | Feb 12, 2008 |
| Priority date | — |
| Expiry date | Mar 16, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L27/34
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
An apparatus of sequentially decoding CCK codes includes a series of received signal registers used to respectively temporarily save the received signals, a phase selector used to select one numeral from 1, −1, j or −j respectively for CCK code of each chip to multiple with the signal register, a series of adders used to sequentially complete adding operation, a series of sequential operation registers used to save values obtained from the sequential selecting operation of the phase selectors and the sequential adding operation of the adders, and a comparing device used to select a maximal value from those saved in the operation registers. The comparing device includes a comparator and a maximum register. According to the invention, the data processing speeds up while the hardware complexity is reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.