Low-latency packet processor
US7330900B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 3, 2002 |
| Grant date | Feb 12, 2008 |
| Priority date | — |
| Expiry date | Jul 1, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04M7/006
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Packets of real-time media streams are processed at a network node such within a desired maximum latency less than the frame interval of the streams. The media streams have respective packet rates all substantially equal to a nominal packet rate and respective packet arrival times that are generally non-deterministic. The streams are assigned to digital signal processors (DSPs), each capable of processing up to a predetermined maximum number of the streams within real-time constraints. The number of streams assigned to each DSP is less than the predetermined maximum number and no greater than the quotient of a desired maximum processing latency less than the frame interval and the DSP processing latency for a single packet. For example, if the desired maximum processing latency is 5 ms. and the processing latency for one packet is 1.6 ms., then only three streams are assigned to a DSP (5/1.6˜3), even if the DSP can process many more than 3 streams in real time. The technique can also be applied to groups of streams whose respective packet arrival times are generally deterministic. Different groups can be processed by a DSP without incurring an entire frame interval of latency, pote…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.