Cache control method and processor system
US7330961B2 · kind B2 · utility
5Cited by
8References
16Claims
0Family size
Assignee
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Key dates
| Filing date | Dec 13, 2004 |
| Grant date | Feb 12, 2008 |
| Priority date | — |
| Expiry date | Dec 3, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/1063
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A cache control method controls data sharing conditions in a processor system having multi-level caches that are in an inclusion relationship. The cache control method indexes an upper level cache by a real address and indexes a lower level cache by a virtual address, and prevents a real address that is referred by a plurality of different virtual addresses from being registered a plurality of times within the same cache. A plurality of virtual addresses are registrable within the upper level cache, so as to relax the data sharing conditions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.