Dynamic instruction sequence selection during scheduling
US7330962B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 14, 2005 |
| Grant date | Feb 12, 2008 |
| Priority date | — |
| Expiry date | Apr 6, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F8/445
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A list scheduler in a compiler can select from a plurality of alternative instruction sequences for one or more computation performed within an application. A scheduler can initially identify and track one or more computations for which multiple alternative instruction sequences exist. An available instruction list can be populated with the alternative instruction sequences. The list scheduler can access the available instruction list during scheduling of the application. The list scheduler can perform a cost analysis while scheduling the instructions by performing a look ahead. The list scheduler may select alternate instruction sequences for similar computations occurring in different portions of the application based on the cost benefit analysis.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.