Match circuit for performance counter
US7331003B2 · kind B2 · utility
1Cited by
10References
25Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 6, 2003 |
| Grant date | Feb 12, 2008 |
| Priority date | — |
| Expiry date | Feb 3, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2201/88
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one embodiment, the invention is directed to a match circuit for implementation in a general purpose performance counter (“GPPC”) connected to a bus carrying debug data. The match circuit comprises logic for activating a match signal when a selected N-bit portion of the debug data matches an N-bit threshold for all bits selected by an N-bit match mask (“mmask”).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.