Method and system for enhancing circuit design process

US7331029B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Niv Amit · Givat Shmuel, IL
• Ronit Bustin · Raanana, IL
• Lidor Goren · Netanya, IL
• Omer Heymann · Even Yehuda, IL
• Moshe Leibowitz · Haifa, IL
• Gil Noy · Ramat Gan, IL
• Alex Raphayevich · Kiryat Ekron, IL
• Maya Speiser · Nes Ziona, IL

Key dates

• Filing date: Sep 22, 2005
• Grant date: Feb 12, 2008
• Expiry date: Feb 22, 2026

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F2119/12
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

A method is provided for designing an integrated circuit. The method includes inserting wire model objects into the schematic of said circuit based on sizing and placement of components of the circuit, and performing an early timing analysis on said schematic. The steps of inserting and performing are repeated after re-sizing and/or re-placing the components if early timing analysis fails.