Method of forming alignment marks for semiconductor device fabrication
US7332405B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 3, 2005 |
| Grant date | Feb 19, 2008 |
| Priority date | — |
| Expiry date | Sep 22, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor integrated circuit is fabricated in a substrate having a semiconductor layer and an underlying insulator layer. The fabrication process includes a step of locally oxidizing the semiconductor layer to form a field oxide, during which step the semiconductor layer is protected by a nitride film. The nitride film has both openings to permit local oxidization in the integrated circuit area, and an opening defining an alignment mark adjacent to the circuit area. The alignment mark may be formed either in the semiconductor and insulator layers, or in a part of the nitride film left after the nitride film is removed from the circuit area. In either case, the edge height of the alignment mark is not limited by the thickness of the semiconductor layer. Using the nitride layer to define both the alignment mark and the field oxide reduces the necessary number of fabrication steps.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.