Thin film transistor array panel and liquid crystal display
US7332743B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 13, 2005 |
| Grant date | Feb 19, 2008 |
| Priority date | — |
| Expiry date | Sep 13, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/60
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
A thin film transistor array panel is provided, which includes an insulating substrate, a gate line formed on the insulating substrate, a gate insulating layer covering the gate line, a data line formed on the gate insulating layer, a lower passivation layer covering the data line, an upper passivation layer formed on the lower passivation layer and made of organic insulating material, and a pixel electrode formed on the upper passivation layer. The thicknesses of the gate insulating layer, the lower passivation layer, and the pixel electrode are respectively represented as dG, dP, and dI, the refraction indexes of the gate insulating layer, the passivation layer, and the pixel electrode are respectively represented as nG, nP, and nI, and condition equations are satisfied according to: 4(dGnG+dPnP)=, which is an even multiple of the wavelength; and 4dInI=, which is an even multiple of the wavelength.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.