On-chip resistor calibration apparatus and method
US7332904B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 28, 2005 |
| Grant date | Feb 19, 2008 |
| Priority date | — |
| Expiry date | Jan 28, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/209
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An on-chip resistor is calibrated with a sense circuit that compares a resistance associated with an off-chip resistor to the on-chip resistor via a current-mirror circuit and a comparator. A digital counter circuit evaluates the comparison and adjusts its count such that a variable digital control signal is provided to the on-chip resistor circuit. During the calibration of the on-chip resistor circuit, the resistance of the on-chip resistor can be matched to the resistance of the off-chip resistor according to a scaling factor (e.g., 1×, 2×, 2.5×, 10×, etc.) as may be desired. Once the resistance associated with the on-chip resistor circuit is sufficiently adjusted, another on-chip resistor (e.g., a terminating resistor of another circuit) can be adjusted from the counter value. Various other circuits can be disabled during the calibration of the on-chip resistor such that additional sources of error (e.g., supply variation, ground bounce, noise, etc.) are minimized.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.