Circuit for compensating for the declination of balanced impedance elements and a frequency mixer
US7332933B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 31, 2006 |
| Grant date | Feb 19, 2008 |
| Priority date | — |
| Expiry date | Jul 31, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03D2200/0088
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Provided is a circuit for compensating for the declination of balanced impedance elements and a frequency mixer. The compensation circuit compensates for a difference between impedance measured at first and second impedance elements, and comprises first and second impedance circuits. The first impedance circuit transforms a first impedance value into a fine impedance value having 2n steps in response to n lower bits of a control signal having k bits. The second impedance circuit transforms a second impedance value into a coarse impedance value having 2m steps in response to m upper bits of the control signal. The first and second impedance values are measured at the first and second impedance elements, respectively, and k is equal to m plus n. The impedance difference between the impedance elements is linearly regulated.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.