Gate leakage insensitive current mirror circuit
US7332965B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 19, 2006 |
| Grant date | Feb 19, 2008 |
| Priority date | — |
| Expiry date | Jul 29, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2203/5031
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A gate leakage insensitive current mirror circuit including an input stage, an output stage, and a pair of complementary source followers. The pair of complementary source followers is connected between the input stage and the output stage. In operation, the input stage receives an input current and the pair of complementary source followers receives a first current source and a second current source. The output stage then provides an output current. The complementary source followers form a negative feedback loop and establish a bias voltage for the input stage and the output stage as a function of the input current that is independent of gate leakage between the input stage and the output stage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.