Dual mode sample and hold circuit and cyclic pipeline analog to digital converter using the same
US7333039B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 2, 2006 |
| Grant date | Feb 19, 2008 |
| Priority date | — |
| Expiry date | Oct 2, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/403
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A cyclic pipeline analog to digital converter includes a dual mode sample and hold circuit, a multiplying digital to analog converter (MDAC), a sub-analog to digital converter (sub-ADC) and a decoder. The dual mode sample and hold circuit has a charge-redistribution mode and a flip-around mode. The dual mode sample and hold circuit receives first and second input voltages and first and second feedback voltages and generates a differential output signal pair. The MDAC receives the differential output signal pair and a digital multiplying word and generates the first and second feedback voltages. The sub-ADC receives the differential output signal pair and generates the digital multiplying word and a digital output word. The decoder converts the digital output word to a digital output corresponding to the first and second input voltages.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.