Phase controlled high speed interfaces
US7333390B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 28, 2005 |
| Grant date | Feb 19, 2008 |
| Priority date | — |
| Expiry date | Nov 28, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00052
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method are used to allow high speed communication between a chip and an external device. The system and method include a PLL with multiple phased outputs configured to be controlled digitally, a deskew PLL configured to align a clock of controller circuitry to interface circuitry, and a phase interpolated voltage controlled delay line configured to phase shift incoming signals. Analog design techniques of phase interpolation accurately position clocks and strobe signals that are required for high speed interfaces. The high speed interface is for transmitting and receiving signals from the external device, for example, a DDR DRAM.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.