Full duplex transceiver
US7333448B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 3, 2003 |
| Grant date | Feb 19, 2008 |
| Priority date | — |
| Expiry date | Feb 18, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L5/1423
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
The invention includes a full duplex transceiver for transmitting and receiving communication signals. The transceiver includes 1 to N sample and hold circuits. Each sample and hold circuit receives a first signal that includes a far-end signal, and in some cases an echo signal, and in some cases alternatively or additionally cross-talk signals. The transceiver additionally includes a plurality of subtraction circuits. Each subtraction circuit receives an output of at least one of the sample and hold circuits. Each subtraction circuit subtracts at least a fraction of a replica signal from at least a fraction of the output of the at least one of the sample and hold circuits. The subtraction circuits generate an output that represent the far-end signal with substantially reduced echo and/or cross-talk interference, and is available for additional receiver processing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.