Digital phase locked loops for packet stream rate matching and restamping
US7333468B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 16, 2005 |
| Grant date | Feb 19, 2008 |
| Priority date | — |
| Expiry date | Aug 1, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L2207/50
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A packet stream multiplexer may include one or more control loops (e.g., digital phase locked loops) for tracking the source clock frequency associated with a packet stream. A first control loop may slowly drive an error between a received timestamp and an estimated timestamp to zero. A second control loop may more quickly drive a first derivative of the error to zero. The second control loop may include a set of digital filters ordered according to tracking speed. The output of the slowest filter is initially selected for updating the source clock frequency estimate. As time progresses, the faster filters are selected in succession. The estimated source clock frequency is used to restamp packets of the packet stream as they are sent out onto an output channel.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.